Question about Monitor

--- Quote Start ---

Monitors can be synthesized but not recommended right?

--- Quote End ---

You're missing the point. The task of a monitor is to confirm that components adhere to the bus protocol specification. If a component will violate the bus specification, then its likely the bus will lock-up, and your system will freeze. Sure you can have a watch-dog reset the bus, and perhaps have a 'reset reason' and a backtrace. But all this can be reproduced in the simulation much easier. You setup randomized bus transactions, and code coverage, etc., and make sure things are well tested. Then you can synthesize.

--- Quote Start ---

I will do some reading and get back to you about this.

--- Quote End ---

Sure. I'm not saying they don't exist, but the question is what use are they? Feel free to come up with a good reason :)

--- Quote Start ---

I have just started Qsys a few weeks ago, apart from the tutorials provided by qsys are there any other online tutorials/ good books about qsys.

--- Quote End ---

You will learn best by building components, constructing _hw.tcl files, and synthesizing them. The nice thing about this approach is that you can get Quartus to generate an _hw.tcl file for some simple components, and then read the documentation about the settings. Things will make much more sense then.

The Quartus handbook has chapters on Qsys. I think alot of the component stuff is the same as the SOPC Builder stuff, so you can look at that manual too.

The Qsys tutorial has layers of hierarchy, since Altera wants to show off the new features of Qsys relative to SOPC Builder. Rather than using that to learn from, try to create a design with an Avalon-MM BFM master, and an Avalon-MM slave registers interface; don't use the PIO core, write your own. Then write a SystemVerilog testbench to generate read/write transactions to your registers.

You can add an Avalon-MM monitor into your testbench, and then generate transactions that violate the bus specification, eg. perform a read or write with invalid byte enables and see the assertion failure messages. You must have a tool that supports System Verilog Assertions (SVA), like the full version of Modelsim, otherwise you will not get the SVA messages.

Cheers,

Dave