Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Question about LVDS!

I am designing a board which contains two cyclon III FPGA(EP3C120). And I want to use LVDS as the communication interface between the two chips and I use the megacore, ALTLVDS. My problem is: how many pairs of differential siganl lines should be used to achieve 1GByte/s speed in one direction? Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Refering to the Cyclone III Users Guide.

    Volume 1 - Section II - Chapter 8 - page 8-1 (March 2007)

    LVDS receive at 875 Mbits / sec (all sides)

    LVDS transmit at 840 Mbis / sec on left and right sides.

    The limiting factor them is the transmiter speed of 840 Mbits / sec.

    If you derate this to 800 Mbits / sec.

    it would take 8 of them to get 8 MBytes / sec.

    10 of them would give you 1 GBytes / sec.

    (9 will not get you there.)

    That is the minimum.

    I would make life simple if I had the IO and go with 16 @ 500 Mbits /sec if I had the I/O as this might make it easier to group and ungroup the signals internally.

    You call.

    Avatar