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I need to send data continously at 2Gbps from FPGA to CMOS chip.
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Serial data streams usually have some form of protocol layered on them, so that the receiving device can determine where data starts, and how to regenerate bytes from the serial stream. How does the CMOS device determine the clock of the serial stream, is it separate, or does it recover the clock from the serial stream?
You need to determine that information first.
You would most likely need to use a high-speed transceiver in 'basic' mode, where you control the serial protocol completely - and you would write code to match the protocol expected by the CMOS camera.
Cheers,
Dave
Honored Contributor
