Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYou get the error, because you are using unsuitable data types and incompatible libraries.
There are two possible ways: - You can refer to the legacy non-IEEE STD_LOGIC_UNSIGNED library. But then you have to import STD_LOGIC_ARITH instead of NUMERIC_STD. bit_vector has to be changed to std_logic_vector in addition - You can use correct VHDL types and the official IEEE.NUMERIC_STD library. The involved signals should be defined as unsigned in this case. As a side remark, the inplemented left-shift can be simply written asvar9 <= var3 & '0'; without involving numeric types.