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Altera_Forum's avatar
Altera_Forum
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14 years ago

question about arithmetic operator '+'

Every time I try following code, there is a error saying that "Error (10327): VHDL error at Arithmetic.vhd(35): can't determine definition of operator ""+"" -- found 0 possible definitions", Can anyone shed some light? Thanks.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.numeric_std.all;

entity Arithmetic is

port(

var3 : in bit_vector(7 downto 0);

var9 : out bit_vector(8 downto 0)

);

end Arithmetic;

architecture architecture of Arithmetic is

signal var8 : bit_vector(8 downto 0);

begin

var8 <= '0' & var3;

var9 <= var8 + var8;

end architecture;

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You get the error, because you are using unsuitable data types and incompatible libraries.

    There are two possible ways:

    - You can refer to the legacy non-IEEE STD_LOGIC_UNSIGNED library. But then you have to import STD_LOGIC_ARITH instead of NUMERIC_STD. bit_vector has to be changed to std_logic_vector in addition

    - You can use correct VHDL types and the official IEEE.NUMERIC_STD library. The involved signals should be defined as unsigned in this case.

    As a side remark, the inplemented left-shift can be simply written as 

    var9 <= var3 & '0';

    without involving numeric types.