Question about AltLVDS megafunction and BLVDS

The send/reveive control and BLVDS output enable has to managed in your application. The soft LVDS core should be able to interface BLVD I/O standard, I'm not sure about the didicated hardware SERDES blocks of Stratix and Arria. Simply set up a test design.

Thank you for your fast response,FvM:-) So I need both TX and RX block for every node.In the other words the ALTLVDS is an SERDES and Physical IO core,right? I notice that this core must have the CLK input,is it possible to provide the clk by each node seprately or I should have a APP to recover the CLK?

The problem of needing a clock with synchronous data transmission hasn't particularly to do with BLVDS. A common clock must be provided in any case. Cyclone III doesn't have a clock recovery option, however. For lower speeds up to several 10 MBit/s, an UART protocol can be a solution.

Clearly,thank you!:)