Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Questıons about VIC on Nios II

Hi I would like to ask about some beginner questions on VIC since I'm new to FPGA. I read Vectored Interrupt Controller section of reference manual couple of times but could not yet assure if swit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Not sure that this AN is still relevant (it is dated), but it's how the VIC/EIC used to work...at least.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an595.pdf

What I gather from this AN is that at least one shadow register set would be necessary for any of the HAL functions to work properly with VIC/EIC. Do you have a shadow register set (at least one) enabled?

The caveat here is that this AN is quite dated and things "may" have changed between then and now. Take a look at the# defs in the existing HAL code. It should give you a good idea of how you deal with this. It is quite a bit different than standard IRQs on Nios II. The standard method is that any exception (IRQ or otherwise) dumps you into the same exception "funnel" (single address where exception code resides).

Read a bit on VIC/EIC and you'll see it's not at all the same.

Regards,

slacker