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Altera_Forum's avatar
Altera_Forum
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10 years ago

Questıons about VIC on Nios II

Hi

I would like to ask about some beginner questions on VIC since I'm new to FPGA. I read Vectored Interrupt Controller section of reference manual couple of times but could not yet assure if switching from internal interrupt controller to VIC based hw design requires additional implementation on SW side.

I'll try to make myself clear with describing my setup

- I implemented an eclipse project using periodical timer interrupts - alarm call back function - to verify if I can configure int's in my environment. And result is alarm call back fnc. is executed whenever given nticks have elapsed. Debugging via jtag showed me that call back is called from interrupt context therefore I have enough information to switch to VIC configured HW design

-In VIC configured design , alarm call back is never called. In addition to this also JTAG Uart does not work too unless I enable reduced driver mode and polling mode consequently.

-I'm using RTOS timer for system clock and Test timer for time stamps.

-My assumption is that SW should not be modified when VIC configuration is enabled. Underlying hw should automatically transfer required interrupts information to cpu and cpu should transfer it to sw.

Do you agree with my assumption ? How can I verify if hw design is working as expected ?

Thank you

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Not sure that this AN is still relevant (it is dated), but it's how the VIC/EIC used to work...at least.

    https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an595.pdf

    What I gather from this AN is that at least one shadow register set would be necessary for any of the HAL functions to work properly with VIC/EIC. Do you have a shadow register set (at least one) enabled?

    The caveat here is that this AN is quite dated and things "may" have changed between then and now. Take a look at the# defs in the existing HAL code. It should give you a good idea of how you deal with this. It is quite a bit different than standard IRQs on Nios II. The standard method is that any exception (IRQ or otherwise) dumps you into the same exception "funnel" (single address where exception code resides).

    Read a bit on VIC/EIC and you'll see it's not at all the same.

    Regards,

    slacker