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Altera_Forum's avatar
Altera_Forum
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8 years ago

Query regarding Simulation in Modelsim

Dear friends, I have a query regarding simulation in Modelsim, I want to take a flop of a input signal to introduce a one clock cycle delay, but I didn't get one clock cycle delay in Modelsim....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

That will be because you're using absolute time delays in the driver, and not synchonising with the clock. Hence the assignmenst to RxD happen just before the clock edge occurs, and it appears to be an immediate transfer. I suggest using @(posedge clk) in the driver: 


always
begin
RxD = 1'b0;
repeat(10) @(posedge clk);
RxD = 1'b1;
repeat(10) @(posedge clk);
end

I removed the final assignment to 0 as this was ignored - it is an always block and loops forever.