Quartus8.1 Warning: A strange waring

Recently when I open a revision project in Quatus 8.1,which I founded in the Quartus7.2,there is a strange waring appears:

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details.

But this is the only one warning after the whole compilation, I didn't see any other warings in the messages.Moreover, I have already assigned all the pins in the Pin Planner that I used.

When I turned to Quartus8.1 Help, it says that :

CAUSE:There are one or more pins with incomplete I/O assignments. The I/O Assignment Warnings report section in the Fitter compilation report lists the affected pins and the missing I/O assignments.ACTION:Use the Assignment Editor or the Pin Planner to add the missing I/O assignments to the affected pins.

I searched the messages, but didn't found anything that I can used to correct my setting.

The device that I used is Cyclone III EP3C10E144c8, I used the classic timing analyzer for timing analysis in the design(with no constraints),and I nearly did not make any changes to the QuartusII default settings.

I have searched the problem for about four days, but I still didn't get anything.

Yesterday, I have download a design examples from Altera web site:

http://www.altera.com/literature/lit-an.jsp,

AN 522: Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices.

I have complied the design examples on my computer in QuartusII 8.1, and I still found the waring that I mentioned.

I don't know why?

I would be very grateful if anyone could give me some suggestions.