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approx. 64uF, split across 16 or so caps.
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Approx. 4uF per cap - what are these caps? Do you have any low value, low ESR ceramic caps as well? Cyclone V devices, particularly the PLL rails, won't tolerate much noise. A LDO will help but only if it has sufficient decoupling close to the appropriate FPGA power pins.
Have you tried any other PLL configurations? Reduce the multiplier.
Finally, in line with comments from lars, have you followed all the Cyclone V connection guidelines? See
cyclone® v device family pin connection guidelines (
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/pcg-01014.pdf). An incorrect or missing RREF_TL resistor is a very likely candidate.
Cheers,
Alex
Honored Contributor
