Quartus v14.0 Altera_PLL IP targeting Cyclone V (5CEFA7) does not lock

is this a custom board?

did you checked the reference resistor for pll?

from pin connection guideline:

Reference Pins

RREF_TL - Input Reference resistor for transceiver and PLL:

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that

side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may

connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace

from this pin to the resistor needs to be routed so that it avoids any aggressor signals.