Quartus Prime that automates the task We're building a complex SoC design targeting an Agilex 7 device and need to integrate multiple IP cores with custom logic. What is Quartus Prime Platform Designer, and what are its key capabilities for system-level integration?

Platform Designer is Altera's system integration tool built into Quartus Prime, and it's the primary way to assemble IP-based hardware systems for Agilex 7 designs. Here's a thorough breakdown of what it does and how it fits into your design flow.

What Platform Designer Is

Platform Designer is a system integration tool included as part of the Quartus Prime software. It captures system-level hardware designs at a high level of abstraction and automates the task of defining and integrating customized HDL components — including IP cores, verification IP, and other design modules. Platform Designer

Core Capabilities

• Platform Designer simplifies the task of defining and integrating custom IP components (IP cores) into your FPGA design. It automatically creates interconnect logic from high-level connectivity that you specify, eliminating the time-consuming task of specifying system-level HDL connections. Creating a System with Platform Designer



• Platform Designer also supports integration of IP cores from third-parties, or custom components that you define. Creating a System with Platform Designer



• Platform Designer allows you to create your own custom components using the component editor. Agilex 7 · Quartus/Tools



• Platform Designer automatically generates the system interconnect fabric to connect the components in the system. Agilex 7 · Quartus/Tools



• Whenever a master port is connected to a slave of a different data width, Platform Designer inserts adapter logic to translate between them. Agilex 7 · Quartus/Tools

Supported Interface Standards

Platform Designer supports Avalon®, AMBA® 3 AXI (version 1.0), AMBA® 4 AXI (version 2.0), AMBA® 4 AXI-Lite (version 2.0), AMBA® 4 AXI-Stream (version 1.0), AMBA ACE5-Lite, and AMBA® 3 APB (version 1.0) interface specifications. Optimizing Platform Designer System Performance

Even though Altera FPGA uses Avalon® as the standard bus interface, Platform Designer supports multiple AMBA® AXI interfaces. Platform Designer also makes migration easier by allowing conversion from Avalon® to AMBA® AXI interface via AMBA® AXI Agents and AMBA® AXI translators. Platform Designer System Integration Tool

Key Feature Set

• Create and reuse components — define and reuse custom parameterizable components in a Hardware Component Definition File (_hw.tcl) that describes and packages IP components. Creating a System with Platform Designer



• Incremental generation — optimize and generate IP components incrementally. Avalon® to AXI interconnect — Platform Designer generates appropriate types of interconnect logic to handle protocol differences. Creating a System with Platform Designer



• Hierarchical system support — generates a separate .ip file that isolates the system from the IP component parameterization, allowing you to change parameters of a single IP component without regeneration of other IP components. Creating a System with Platform Designer



• Command-line support — optionally use command-line utilities and scripts to perform functions available in the Platform Designer GUI. Creating a System with Platform Designer



• Up to 64-bit addressing, with optimization of interconnect and pipelining within the system and auto-adaptation of data widths and burst characteristics. Creating a System with Platform Designer

Hierarchical Design Support

Platform Designer supports hierarchical systems that include one or more Platform Designer subsystems within another Platform Designer system. Platform Designer allows you to create, explore, and edit systems and subsystems together in the same Platform Designer window, and generates the complete system hierarchy during the top-level system's generation. Managing Hierarchical Platform Designer Systems

In a team-based hierarchical design flow, you can divide large designs into subsystems and allow team members to develop subsystems simultaneously. Managing Hierarchical Platform Designer Systems

You can use hierarchy to sub-divide a system into smaller subsystems that you can then connect in a top-level Platform Designer system. Additionally, if a design contains one or more identical functional units, the functional unit can be defined as a subsystem and instantiated multiple times within a top-level system. Using Hierarchy in Systems

Security Features

Platform Designer interconnect supports the Arm® TrustZone® security extension. The Platform Designer Arm® TrustZone® security extension includes secure and non-secure transaction designations, and a protocol for processing between the designations. Configuring Platform Designer System Security

Primary Output Files

• Platform Designer Design File (.qsys) — contains the hardware contents of the Platform Designer system. Agilex 7 · Quartus/Tools



• Platform Designer Information File (.sopcinfo) — contains an XML description of your Platform Designer system. Agilex 7 · Quartus/Tools



• Hardware description language (HDL) files — are the hardware design files that describe the Platform Designer system. The Quartus Prime software uses the HDL files to compile the overall FPGA design into an SRAM Object File (.sof). Agilex 7 · Quartus/Tools



• Platform Designer also generates HDL files for the system and the Quartus Prime IP File (.qip) that provides the list of required HDL files for the Quartus Prime compilation. Agilex 7 · Quartus/Tools

Integration into the Quartus Prime Design Flow

After you construct your system using Platform Designer, and after you add any required custom logic to complete your top-level design, you must create pin assignments using the Quartus Prime software. Agilex 7 · Quartus/Tools

To complete the hardware design, you need to: instantiate the Platform Designer system module in the Quartus Prime project, assign FPGA device and pin locations, compile the Quartus Prime project, and verify timing. Agilex 7 · Quartus/Tools

Simulation and Verification

You can simulate a custom component with Platform Designer and the Avalon Verification IP Suite. Agilex 7 · Quartus/Tools

Platform Designer generates a testbench system when you enable the "Create testbench Platform Designer system" option. Agilex 7 · Quartus/Tools

You can use the System Console to perform low-level debugging of a Platform Designer system. Agilex 7 · Quartus/Tools

Agilex 7 SoC-Specific Usage

At the center of the SoC design example is the Platform Designer system. Agilex · General For Agilex 7 SoC designs specifically, in Platform Designer, you open the Hard Processor System IP parameter editor Agilex 7 · IP-cores to configure the HPS subsystem, making Platform Designer the central tool for both soft-IP integration and HPS configuration in Agilex 7 SoC designs.

In summary, Platform Designer is the hub of the Agilex 7 hardware design flow — it handles IP instantiation, interconnect generation, address mapping, clock/reset management, security configuration, hierarchical design, and simulation setup, all feeding into a Quartus Prime compilation.