Quartus Prime Lite - Difficulties with simulation

Hi,

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Thanks very much for taking the time to verify that it doesn't work! It would have been simple to have left it without trying the 10 LP and ALTPLL, and I would have spent a bunch of time fruitlessly trying to replicate your results in my environment. I'm glad to know that I'm not (completely) crazy or a (complete) moron. :)

Any suggestions for tricking a testbench into generating the PLL output clock without changing the synthesized code? I suppose I could just create a version with an input clock to the FPGA that replaces the PLL output for functional testing, but the timing would likely be totally whacked.

And please advise on the estimated timeframe for the simulator fix. I know that's asking a lot.

Thanks again!

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Yes we acknowledged this bug/issue and has been reported to the engineering team.

however you can run cyclone 10 lp altpll vhdl simulation model in quartus v17.0 and v17.1.

it works fine

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)