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EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Quartus joins two RAMs?

In my design I deliberately designed two dual-port RAMs of single M9K block each, using them through both ports A and B in parallel. I spent several days debugging the application I am designing fa...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Eugeny,


1. May I know what device you are targeting and Quartus version used?

2. I can see the code snippet provided, could you try to provide a design and achieve it here .qar. I will try to reproduce it at my end. You can email or private message me if it is confidential.


Thanks,

Regards


EugenyB's avatar
EugenyB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello, I am using Cyclone 3, Quartus versions tried are 12.0 SP2 and 13.0 SP1.

As a starting point I have put the definition of RAMs in one of my replies above, and briefly said how I used them. Putting code here is not appropriate as it is relatively big. The data being addressed through the address wires are in the first part of RAM, address MSb is always 0.

How can I send you a private message? Suspect that when I click your anonymous icon I must see something useful, but there's only progress indicator rotating.

Is your email address "SyafieqS_Intel@intel.com"? Who I am talking to?