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Altera_Forum
Honored Contributor
Honored ContributorQuartus II tools for SoC FPGAs
Hi, for an university project I started developing for a soc FPGA board. I want to integrate some crypto IP cores for certain algorithms, and compare how they perform. Since I'm really new to develop...
Altera_ForumHonored Contributor
Honored ContributorIt is often much easier to debug your Avalon interface issues in simulation than in hardware.
My recommendation would be to construct a good testbench for your component(s) using the Altera supplied verification IP: http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf
