Forum Discussion
5 Replies
- Altera_Forum
Honored Contributor
The image is too small to see what you're seeing. Can you make it bigger?
- Altera_Forum
Honored Contributor
Hi there,
Basically, the Covert Programming File window failed to let me add an SOF file. Also, the dialog box mentions something like the following: "File !@#$%^&*()_.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires..." So, what should I do now ?? Thanks, TH - Altera_Forum
Honored Contributor
FPGA configuration files containing time limited IP are for evaluation with direct JTAG connection only and don't run when loaded from configuration memory. Thus generating jic file is useless. Quartus programming file converter knows about and stops operation.
- Altera_Forum
Honored Contributor
Two choices. 1. Load with JTAG. 2. Get a license so that it doesn't generate a time limited sof.
Dave - Altera_Forum
Honored Contributor
Thanks guys. I know what to do now. Have a nice day...