Quartus II 12.0 : Timing closure and register retiming

I am new to FPGA programming and quartus.

I am unable to fix the timing closure issue. I get “Worst case slack is -3.038”.

I am trying to make use of register retiming using a pipelined multiplier.

mult.v

module mult (out, clk, a, b);

output [15:0] out;

input clk;

input [7:0] a;

input [7:0] b;

reg [7:0] a_reg1;

reg [7:0] a_reg2;

reg [7:0] b_reg1;

reg [7:0] b_reg2;

reg [15:0] out;

wire [15:0] mult_out;

assign mult_out = a_reg2 * b_reg2;

always @ (posedge clk)

begin

a_reg1 <= a;

a_reg2 <= a_reg1;

b_reg1 <= b;

b_reg2 <= b_reg1;

out <= mult_out;

end

endmodule

I have followed quartus handbooks guidelines:

1. User can insert an extra bank of registers at the input and allow the retiming feature to move the registers for better results.

2. Turn off the auto shift register replacement for registers that control pipeline stages.

3.# set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg ( I am not sure of the way to do this).

timing constraints are

mult.sdc

create_clock -name clk -period 4.000 [get_ports clk]

set_input_delay -clock clk 0.1 [all_inputs]

Set_output_delay -clock clk 0.1 [all_outputs]

Following tcl script is used to check the result:

mult.tcl

load_package project

load_package flow

load_package report

load_package sdc

set top mult

project_new -overwrite mult

set_global_assignment -name FAMILY "Cyclone IV GX"

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_global_assignment -name VERILOG_FILE mult.v

set_global_assignment -name SDC_FILE mult.sdc

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

export_assignments

execute_module -tool map -args "--enable_register_retiming=on"

execute_module -tool fit

execute_module –tool sta

map report has

Info (13086): Performing gate-level register retiming

Info (13093): Not allowed to move 32 registers

Info (13094): not allowed to move at least 32 registers because they are in a sequence of registers directly fed by input pins

Info (13089): The Quartus II software applied gate-level register retiming to 0 clock domains

How to inform quartus that the registers (pipelining control regs) must be used for retiming so that timing constraints are met?

Please let me know your suggestions to fix register-retiming and timing closure.

Thanks & Regards,

Upadyaya