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New ContributorQuartus: How to debug why Synthesis is eliminating logic from the design
Hi,
basically unexpected removal of logic suggests a design error, may be wrong logic condition, missing clock or part of the design unintenionally held in reset.
Problem is, if a complete logic chain is removed in synthesis, it's not easy to see where it's broken. Creating auxiliary output or keeping debug signals with respective synthesis attributes (e.g. noprune for registers) and watch them in Signaltap is a possible option. Diagnosis is probably simpler in RTL simulation.
RegardsFrank
Super ContributorHi,
basically unexpected removal of logic suggests a design error, may be wrong logic condition, missing clock or part of the design unintenionally held in reset.
Problem is, if a complete logic chain is removed in synthesis, it's not easy to see where it's broken. Creating auxiliary output or keeping debug signals with respective synthesis attributes (e.g. noprune for registers) and watch them in Signaltap is a possible option. Diagnosis is probably simpler in RTL simulation.
Regards
Frank
