Quartus doesnt recognize my FSM as a FSM

I always use the two-process approach for state machines as that allows you to generate both combinatorial and registered outputs. If you use a one -process state machine all signals are clocked and often you can 'loose' active clock cycles due to this approach.

It however pays to generate 'enables' in the combinatorial section and use these in the clocked section to register values. It saves on LE's and makes nicer RTL diagrams as well.

using 'hold' signals generates a lot of extra muxes, which eventually generates slower logic.