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syam's avatar
syam
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Quartus 18.1 - CYCLONE V Preloader issue

Hi Am working on a project with CYCLONE V - 5CSXFC6D6F31C8N with Quartus 18.1. After compilation in emif.xml file in the hand off folder the SDRAM related clock info is being written as 0 by quart...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi syam,


I think it is a bug from the older u-boot from 2013.

Will require to use the latest U-boot to avoid that problem.


Thanks.

Regards,

Aik Eu


  • syam's avatar
    syam
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Thanks. I will try with the new boot flow and revert with my findings. But note again that it is for the latest version of quartus and not for quartus 18.1. So not sure whether I will land on compatibility issues with quartus 18.1 generated files.

  • syam's avatar
    syam
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Migrated my FPGA design to Quartus 20.1.1, compiled and generated the RBF and tested with old 18.1 boot flow. The RBF is working.

    Then I followed the latest boot flow you suggested. Generated the files required. Now right at power up and boot up I am seeing this error.

    I found this article - https://www.intel.ca/content/www/ca/en/support/programmable/articles/000073948.html which points to a similar error. There it is suggested that a bug exist with uboot source code. Also a patch is given. But it seems it is related to Arria10 and not Cyclone V which am working with. But I tried applying it but it didn't get applied. May be because it is intended for Arria10 only.

    Any help would be much appreciated.

    Best Regards

    Syam