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syam
Occasional Contributor
Occasional ContributorQuartus 18.1 - CYCLONE V Preloader issue
Hi
Am working on a project with CYCLONE V - 5CSXFC6D6F31C8N with Quartus 18.1. After compilation in emif.xml file in the hand off folder the SDRAM related clock info is being written as 0 by quart...
syamOccasional Contributor
Occasional ContributorHi Aik
We are using the preloader/uboot source code that shipped with Quartus 18.1. So I would assume this one is correct.
We have a .scr file on the SD card that enables the bridge you are talking about.
We will inspect the frequency shown on uboot log and revert with our findings.
syamOccasional Contributor
Occasional ContributorHi Aik
Here is the bootlog attached. The bridges seems to be registered.
Note that we are able to boot in to Linux. But we are unable to use the 50Mhz from FPGA to run the SDRAM.
