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syam's avatar
syam
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Quartus 18.1 - CYCLONE V Preloader issue

Hi Am working on a project with CYCLONE V - 5CSXFC6D6F31C8N with Quartus 18.1. After compilation in emif.xml file in the hand off folder the SDRAM related clock info is being written as 0 by quart...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi syam,


I cant be sure regarding most of the parameters at the moment.

Does the specic values for DDR clock 118MHz relected in the emif.xml file?

I see that your F2S_SDR_REF clock is 0 KHz even you have set to 50Mhz, I think is because the bridge was not enabled yet.

When in u-boot, you can run the cmd "bridge enabled" and if possible check any changes to the F2S related clock values.


Thanks.

Regards,

Aik Eu


syam's avatar
syam
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi Aik

Thanks for the response. 118MHz is not reflected in the emif.xml file.

The boot log is from the preloader before u-boot.img is loaded. So am not sure how to do the bridge-enabled stuff. Can you please share the procedure to do so.

Best Regards

Syam

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