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syam's avatar
syam
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Quartus 18.1 - CYCLONE V Preloader issue

Hi Am working on a project with CYCLONE V - 5CSXFC6D6F31C8N with Quartus 18.1. After compilation in emif.xml file in the hand off folder the SDRAM related clock info is being written as 0 by quart...
syam's avatar
syam
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi

The image you have sent cannot be opened.

There is definitively a problem with the preloader generation. I set the clock for the DDR3 from the FPGA at 50Mhz. But the preloader bootloader shows 0.

aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi syam,

Sorry that I am not aware the image is not able to open in the community forum page. I was using another link to upload the image.
Below is the image, refer to the default values of the IP:

You can try to check the hidden parameters of the IP in platform designer to verify again the difference before and after generate.

The hidden parameters can be displayed when right click on the blue gradient part of the pic above.

Thanks.

Regards,

Aik Eu

  • syam's avatar
    syam
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thanks. Can you please point out where the hidden fields relevant to the marked items in the boot log are located ?