Forum Discussion
Altera_Forum
Honored Contributor
11 years agoquartus 12.1 compilation too long using altiobuf in CycloneV
hello, i am using quartus 12.1 Build 177 11/07/2012 SJ Full Version to compile a cycloneV (5CEFA9F31C8) project. the compilation time is beyond 24 hours (still not successfully routed) when i us...
Altera_Forum
Honored Contributor
11 years agoNew Test Results Report: Still compilation too long when using altiobuf with dynamic input delay chain enabled.
Quartus II Version: 14.0.0 Build 200 06/17/2014 SJ Full Version Quartus II 12.1 report internal error, please see my previous post, so we divert to 14.0 to compile the project. As Rysc suggested, we just use IOBUFs to try, and in order not to be synthesized off by quartus, we designed the following project. DATA_RECEIVE_MODULE-->FIFO-->DATA_SEND_MODULE DATA_RECEIVE_MODULE: receive 48 channels ddr data from out side of FPGA; DATA_SEND_MODULE:send out the received data to out side of FPGA. the DATA_RECEIVE_MODULE uses two following fashions: 1. input_pad --> altddio_in : 36 channels 2. input_pad --> altiobuf (with dynamic input delay chain enabled) --> altddio_in: 12 channels The following is the message info printed by Quartus 14.0: http://www.alteraforum.com/forum/attachment.php?attachmentid=10418&stc=1 According to the message, we believe that it again enters into deadlock. Regards, ingdxdy