Qsys

You don't need locked, areset and phasedone conduit signals. You don't need on chip memory and avalon master either. You just need basic pll with your configuration. Connect clock in signal to pll and export the pll output signal and connect it in pin planner. Don't forget entering the input clock's frequency and set the pll frequencies correctly.

The things you have done seem to be ok but you didn't upload the port mappings in code. If you don't connect the pll's output to the entity's output signal it doesn't work.