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Altera_Forum's avatar
Altera_Forum
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12 years ago

Qsys tutorial modelsim simulation problem

Hi, I'm running through the simulation chapter of the Qsys System Design tutorial and i'm running into problems compiling the generated system verilog module. Most of the load_sim.tcl are ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Alex,

You're correct Alex. Altera Tech support helped me with this, just today actually. The problem was with the

vlog -sv ./test_program.sv -L pattern_generator_tb_csr_master

It should be:

vlog -sv ./test_program.sv -L altera_avalon_vip_pkgs_lib

I'm still waiting for an explanation why that fixed it though. I'm about to do a Qsys project and i just want to make sure that all autogenerated files are error free.

Thanks,

Joel