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Altera_Forum's avatar
Altera_Forum
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14 years ago

QSYS, minor glitches with parameterized ports

Encountered some minor glitches in QSYS in regards to vhdl generics in Quartus 11.0sp1. Found workarounds to all of these, but they had me puzzled for a while.

I designed several bus modules with parameterized address and data bus sizes. QSYS complained that the bus size on each of these ports was "-1," despite my having defaults in the VHDL generic section. I hardwired these bus sizes and everything was fine.

(2) Another minor problem I found along the way was that QSYS grabbed the generics from other associated design files after analyzing the files, rather than from the selected top level file. Very confusing. I made sure it had used the correct top level file. The only way I could make this work was to move the other files temporarily to another directory, run the tool, and then move them back.

(3) Finally, after creating a part, I ended up changing a generic from being a real to being an integer. I never could get QYS to recognize the change. Subsequent edits, rescans, exits from QSYS all didn't set the port correct. I ended up (ouch) editing the TCL HW file by hand and that worked.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    If possible I recommend opening a service request and attaching your component so that the tools will be fixed: http://www.altera.com/mysupport -1 is used as a default for a parameter which will get filled in later.

    By the sounds of it the default value is not being filled in correctly. I'm guessing if you add an elaboration callback to the .tcl file you can work around this bug. If you want to see an example take a look at the .tcl files for the read and write masters in this design: http://www.alterawiki.com/wiki/modular_sgdma (verilog based but the .tcl commands will be the same)