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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Qsys Keep generating Verilog files when I want VHDL

How do I get QSYS to stop generating Verilog and start generating VHDL code for my system module. Under the Generation tab I keep selecting VHDL but Somehow it keeps spitting out verilog. Grr..

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Stepmother Altera doesn't love her VHDL-children as much ...

    Altera effectively has turned to using Verilog and System-Verilog and Qsys only generates (System-)Verilog for Altera supplied IP (Avalon components) and connects everything together with Verilog.(System-)

    Unless you want to simulate the Qsys design, this shouldn't pose a problem (I learned to live with it, as beggars can't be choosers).