Thanks, I will go through the handbook you provided.
Looking at the Altera Cyclone 3 Development board handbook, it provides the part number of the SRAM (K1B3216B2E-B170) along with some timing waveforms for read and write to it.
Do I even need to use Qsys to talk between my custom CPU and this SRAM? Should i be able to create a basic controller and connect directly to that external SRAM, or does Qsys provide something I'm not thinking of.
I found an an example of a Qsys generated SRAM controller specifically for the Cyclone 3 Development board on the Altera wiki, but I'm still trying to understand how to actually use it.
What is the library component you are referring to? the SRAM controller?