PS and JTAG

Hi HT, 1. If you refer to Configuration Scheme (Table 8-3, Table 8-4 and Table 8-5 on page 172 Cyclone IV Handbook), you can combine AS, PS and JTAG together on your board. However, when you want to select which configuration scheme you want to use, you need to select the correct MSEL setting on your board. If you look at Intel Cyclone IV Dev kit schematic diagram, you can see how we design MSEL setting on our board. - Download this link & run as Administrator http://fpgadownload.intel.com/outgoing/devkit/12.1/cycloneIVGX_4cgx150_fpga_v12.1.0.exe - Goes to <Installation directory>\kits\cycloneIVGX_4cgx150_fpga\board_design_files\cycloneIVGX_4cgx150_fpga\schematic - Open schematic diagram c4gx_f896_host_b.pdf for more details. 2. Figure 8-13 in Handbook is more accurate. CONF_DONE and nSTATUS for Cyclone IV should be Directional (open-drain) pin. For more information and details regarding pin connection, please refer to Cyclone IV Device Family Pin Connection Guidelines (Configuration/JTAG Pins section) Link for Configuration Scheme Handbook = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf#page=172 Link for Cyclone IV Device Family Pin Connection Guidelines (Configuration/JTAG Pins section) = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf#page=2 I hope this will help. Thanks.