Forum Discussion
New ContributorPS and JTAG combination
New ContributorThanks Anand,
it was really helpful document.
I have one more question:
in Figure 2 in the document you sent, does not talk about pins: nCONFIG, CONF_DONE and nSTATUS connections in MAX10 configuration. I believe I should follow the figure 12 in MAX10 config document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf in page 35 for these pins. Is that correct?
Thanks
Regular ContributorHi,
Yes, you are correct. we can ignore TRST pin for EP4CGX30 FPGA.
The TRST pin is an optional active-low, asynchronous reset input used for Joint Test Action Group (JTAG) boundary-scan testing (BST). While the
TRST pin can be helpful in systems that use it, it is unnecessary for the successful operation of the BST circuitry in Intel devices. download cable does not use this pin.
Regards
Anand
