properly constraining system synchronous interface

The Zero Delay Buffer mode is intended to use the FPGA as a zero delay clock buffer: it makes the clock at the PLL's dedicated output clock pin in phase with the input clock.

The normal compensation mode should give you the best results.

I'm not really sure why Quartus doesn't always use the I/O registers. I suspect it's because it takes a minimum effort timing driven aproach.

You set the timing constraints and it tries to meet them.

If it needs them to meet timing constraints, then it will use them automatically -- and it can be quite clever at it.

If it doesn't need it, it doesn't.

The clock network delay in the FPGAs is pretty much fixed, independently of the number of loads, since the clock network is pre-built.

Why did your timings improve when you replaced your simple square wave with a more realistic logic? No clue.

You can try to compare the paths in the TimeQuest GUI.

There are two ways to ask Quartus to give you extra margin.

The "try and give me some margin" way: set a target slack in the fitter settings.

The "you must give me this" way: add clock uncertainty to your clocks. Or, just for I/O, make the I/O constraints worse.