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Just to explain my understanding of sign of tSU or tH:
tSU & tH at register level are both labeled positive.
When viewed at pins the relationship will either stay if clock and data delay are equal or the timing window(tSU + tH) will shift relative to clock edge and may sit in front of it or behind it. If timing window shifts in front of clock edge then tSU stays positive but tH is now labeled negative. If timing window moves behind clock edge then tSU becomes negative and tH stays positive.
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kaz,
I think our understandings of the tSU and tH parameters match. I interpret your explanation to be the same as the example from Maxim IC.
It's easy to imagine a high speed DAC with parallel data input having a rather elaborate clock distribution network to phase align clock edges to all the data input registers. That distribution network could delay the clock edge enough that the clock needs to reach the pin of the part before the data in order to meet timing, thereby having a negative setup time.
The part I'm using is, I think, the lower speed grade version of a very high speed part. If it is the same chip, then it would have the same distribution network introducing delay in the pin to input register clock.
Honored Contributor
