Honored Contributor
Honored ContributorThanks rbugalho! Enabling the fast I/O register improves my timing margin noticeably. The system I am working on is expected to operate in harsh environments (wide temperature range), so I'll take all the margin I can get.
Before enabling the fast I/O registers, I had a slow/fast clock to output delay range of -0.574/-2.805 nsec. After enabling the registers, that range moved to -1.530/-3.099 nsec, a 0.66 nsec improvement in delay uncertainty. If the dedicated output registers improve timing margin so much, why would they ever be turned off? Power savings? I noticed an interesting bit of behavior that slightly defied my expectations. I set up the PLL in my design in Zero-Delay Buffer mode to achieve the most compensation for clock network and output uncertainty. Initially, I was driving a simple square wave to all outputs with the following Verilog statement: DAC_I_out <= ~DAC_I_out; After I was satisfied that the timing could be met by phase shifting the data with the PLL programmable delay, I replaced the simple square wave with a more elaborate source of data, and recompiled the design. I thought that having a wider fan-out for the global clock from the PLL would slow down the clock and result in slower clock to output delays. However, the opposite happened. The clock to output delays were sped up by ~0.6 nsec. The spread in clock to output delay over PVT was also reduced, so I'll take it. I'm a bit puzzled as to why that parameter would improve when I added logic to the design.
