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Honored Contributor
Honored Contributorproperly constraining system synchronous interface
I'm trying to interface an FPGA to a DAC (running at 200MSa/s) in a system synchronous configuration. The FPGA clock and DAC clock come from the same source and then split on the PCB before going to...
Altera_ForumHonored Contributor
Honored Contributorkarl,
no, you don't have to use DDR to make use of the IOE register. Quartus will automatically pack registers into IOEs when needed (to meet setup requirements) and possible. The Fitter -> Netlist optimization will report it, if so. Some quick tests indicate that Quartus can meet your I/O timing requirements without resorting to I/O register packing, so it might not do it. There should be a Fast I/O register assignment to force it, if you need it.
