properly constraining system synchronous interface

Just to explain my understanding of sign of tSU or tH:

tSU & tH at register level are both labeled positive.

When viewed at pins the relationship will either stay if clock and data delay are equal or the timing window(tSU + tH) will shift relative to clock edge and may sit in front of it or behind it. If timing window shifts in front of clock edge then tSU stays positive but tH is now labeled negative. If timing window moves behind clock edge then tSU becomes negative and tH stays positive.