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Honored Contributor
Honored Contributorproperly constraining system synchronous interface
I'm trying to interface an FPGA to a DAC (running at 200MSa/s) in a system synchronous configuration. The FPGA clock and DAC clock come from the same source and then split on the PCB before going to...
Altera_ForumHonored Contributor
Honored ContributorJust to explain my understanding of sign of tSU or tH:
tSU & tH at register level are both labeled positive. When viewed at pins the relationship will either stay if clock and data delay are equal or the timing window(tSU + tH) will shift relative to clock edge and may sit in front of it or behind it. If timing window shifts in front of clock edge then tSU stays positive but tH is now labeled negative. If timing window moves behind clock edge then tSU becomes negative and tH stays positive.
