Honored Contributor
Honored ContributorI was confused by the negative tSetup value, but found an example from Maxim IC that explains things pretty well. Altera forum won't let me post a link, but if you search the Maxim IC site for "TUTORIAL 4053" it should show up as the top result.
Hypothetically if the tSetup for the data input register in the DAC is 500 psec but there is at least 1.1 nsec of delay through the clock buffer/distribution network on chip, then the tSetup at the package input would be -0.6 nsec (assuming no or equal package pin to chip delays). I double checked the device datasheet and it is definitely -0.6/+2.1 nsec for tSetup/tHold. I assigned the pins so that each bit in my bus is driven from the same I/O bank. Within a bus, the worst case bit-to-bit skew in clock to output delay reported by Quartus is quite good, ~100 psec. There is a second bus, driving another DAC, that I assigned to an adjacent I/O bank. One bus is a row I/O while the other is a column I/O. From bank to bank, Quartus reports an additional ~100 psec skew. I'm pleasantly surprised by that report because the timing spreadsheet indicated a larger difference (8.48 - 5.88 = 2.6 nsec) in bank to bank skew when one bank is row I/O and the other is column I/O. I was thinking I would have to use two PLLs to introduce different phase shifts to the two output banks, but it looks like that is not necessary. On page 6-2 of the Cyclone IV device handbook, I saw the following statement: The IOE contains one input register, two output registers, and two output-enable (OE) registers. The two output registers and two OE registers are used for DDR applications. Can I use the output registers if my design is not a DDR application? When I search the Chip Planner for one of the bits in my data bus, I see four entries with the following resource types: DAC_I_out[0]~reg0 - Register cell DAC_I_out[0]~output - I/O output buffer DAC_I_out[0] - I/O pad DAC_I_out[0]~reg0feeder - Combinational cell The register cell is located in a general purpose region, not the dedicated output block, which tells me I'm not currently packing my output registers into the IOE. How do I specify that? Is it a setting in the Assignment Editor that I missed while reading through the types of assignments? Thanks!
