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Altera_Forum's avatar
Altera_Forum
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13 years ago

properly constraining system synchronous interface

I'm trying to interface an FPGA to a DAC (running at 200MSa/s) in a system synchronous configuration. The FPGA clock and DAC clock come from the same source and then split on the PCB before going to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Should it not be 2.1 ns tSetup and -0.6ns tHold?

I've never seen a negative tSetup...

Anyway, you're in the right path.

A couple of checks:

- Assign your pins and set the correct I/O standard. The delays may change a bit.

- Make sure your output register is being packed into the IOE.