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Altera_Forum's avatar
Altera_Forum
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13 years ago

properly constraining system synchronous interface

I'm trying to interface an FPGA to a DAC (running at 200MSa/s) in a system synchronous configuration. The FPGA clock and DAC clock come from the same source and then split on the PCB before going to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What you are observing is the effect of min/max timing models. That is a rather large difference however. You can improve this somewhat if you make sure that your outputs are all in the same sub-bank of the FPGA. You should be able to find a data valid window that you can capture the output data at 200 MHz in CIV. Are you in the slowest speed grade device? That will also effect output timing.