Altera_Forum
Honored Contributor
15 years agoProhibited of the Cyclone III LS FPGA configuration with an encrypted bitstream.
Hi,
I’m currently using the cyclone III LS FPGA development kit. I have already configured the FPGA with an encrypted bitstream. Thus, I would like to know if it is possible to prohibit the configuration of FPGA with an unencrypted bitstream when an AES key is programmed on the FPGA. I read the Cyclone III handbook that shows available security modes but in the page 9-76 I don’t really understand the meaning of the following sentences: --- Quote Start --- “Secure operation with volatile key programmed and required external battery - this mode accepts both encrypted and unencrypted configuration bitstreams. Use the unencrypted configuration bitstream support for board-level testing only”. --- Quote End --- What do you mean “board-level testing” in my case? Thank you for your help.