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Jcole's avatar
Jcole
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Programming S25FL256 through Cyclone 10 with file from Processor

Hi, I wanted to see if it is possible to load a S25FL256 with a Programming File (.rpd, .pof, .sof, etc) through the Cyclone 10 LP using a file received from the processor. Essentially what I'm t...
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Programmable Logic Device
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
    Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.

FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Jcole,


I'm attempting to grasp the situation better. Could you please provide a block diagram or schematic illustrating the interconnections among the FPGA, processor, and flash?


Regards,

Fakhrul