Forum Discussion
Occasional ContributorProgramming S25FL256 through Cyclone 10 with file from Processor
Hi,
signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.
Regular Contributor
Occasional ContributorHi Fakhrul,
I ran my design through the Cyclone 10 LP Dev Kit with EPCQ128A just to make sure the result was the same. In my design, I use a state machine to set the registers of the GSFI to conduct a WR enable, Write 1 Byte, and Rd One Byte Using the following instructions, but don't get a response from the flash:
WR Enable:
CSR_ADDR 0x7 CSR_WR_DATA 0x00000006
CSR_ADDR 0x8 CSR_WR_DATA 0x00000001
WR 1 Byte:
CSR_ADDR 0x4 CSR_WR_DATA 0x00000000
CSR_ADDR 0x0 CSR_WR_DATA 0x00000101
CSR_ADDR 0x6 CSR_WR_DATA 0x00007002
AVL_ADDR 0x004000 AVL_DATA 0xABCD1234
RD 1 BYTE
CSR_ADDR 0x4 CSR_WR_DATA 0x00000000
CSR_ADDR 0x0 CSR_WR_DATA 0x00000101
CSR_ADDR 0x5 CSR_WR_DATA 0x00000003
AVL_ADDR 0x004000
FvMSuper Contributor
Hi,
signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.- Jcole
Hi FvM,
Even after waiting for quite a while, the the mem_waitrequest is never released after the write to the data address command. Am I still using the core incorrectly?
