Forum Discussion
Programming S25FL256 through Cyclone 10 with file from Processor
- 2 years ago
Hi,
signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.
I would like to have the option to rewrite the 2nd image stored in the flash that is visible to the remote update system. I can receive hex files serially or in bytes from the attached processor with no issue. When trying to explicitly use the Altera_nCS, Altera_Data0, and Altera_dclk pins connected to the FPGA to write to the flash, I get errors in Quartus about using the pins. I figured that I would need to use a built in IP to handle this communication, but from most of the documentation on the IPs they seem to need either a JTAG connection, a console setup, or Quartus to program the flash.