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Altera_Forum
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17 years ago

Programming Problem

Hello,

I'm having a curious problem programming my Cyclone III FPGA over JTAG. Everything was working fine until a couple days ago. Now, when I load a design via JTAG, Quartus claims the programming is successful, but all my IO pins are driven high (like my design didn't even load). Could this be a symptom of a bad FPGA. Perhaps one that got fried somehow? I haven't worked with these that much so I don't really know what they look like when they fail.

Thanks,

Andrew

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    Hello,

    I'm having a curious problem programming my Cyclone III FPGA over JTAG. Everything was working fine until a couple days ago. Now, when I load a design via JTAG, Quartus claims the programming is successful, but all my IO pins are driven high (like my design didn't even load). Could this be a symptom of a bad FPGA. Perhaps one that got fried somehow? I haven't worked with these that much so I don't really know what they look like when they fail.

    Thanks,

    Andrew

    --- Quote End ---

    What kind of board do you use ?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Check the conf_done pin on your FPGA. Is it going to high level at the end of the configuration?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Once I had a similar problem, the fpga were going to reconfigure itself from EPCS "AFTER" I uploaded the program to Nios and so, all the pins were Z.

    at my situation the problem was hiding in SOPC configuration. try to recreate your SOPC and see what happens.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    if u are talking about the unused pins,in quartus gpi,u can go to settings->device&pin options->unused pins and select the state of unassigned pins there but if u are talking about the assigned pins,u should check your vhdl code of those pins' corresponding component and see and set the initial state of those registers.If the initial states are logical low and after programming u see those being high,this means the fpga isn't programmed normally and u should check the component's editor tab in sopc builder by right clicking the component and clicking edit comp.