Programming FPGA, Verilog and Nios softcore

Hi Hani,

Your question is perfectly valid and for a start let us agree on the terminology in this complex setting. You write HDL(VHDL, verilog,…etc) or you import a netlist or you draw schematic then you compile your project and end up with firmware(sof,pof…etc) which configures the switches of FPGAs into a functioning hardware.

(forget for now that some new tools convert C to firmware directly, others C to HDL but are not mature yet. The fate of this C is completely different from C used as source code for nios).

Nios and its peripherals are added as firmware. So when you download the firmware it contains all the necessary configuration data to end up as hardware including that for nios and its peripherals.

After reset, hopefully nios will start running its fetch-execute sequences and will continue for ever.These instructions are the software side(designed originally from a source code e.g. C then compiled into exe). The software instructions are either stored completely inside fpga in the form of mif file(for small programs). Or if it is too large to fit(and usually it is, given the tons of today’s code) then it is split up into two sections: a main software stored in flash(or configuration device) and small bootloader stored inside fpga.

Assuming a company has two friendly engineers; a firmware engineer and software engineer, the procedural work is as follows. The firmware guy builds a nios module in their project, gets ptf file from sopc, emails this ptf to the software guy who builds up their software in the IDE and then emails the bootloader as mif back to the firmware guy who should recompile.If software is too small then the software engineer only needs to send you the mif file and all is done.

The main software program has to be loaded into flash. Interestingly, the software can be used to download “itself” into flash . You run a temporary version of software using sof and use any soft skills as usual including dowloading firmware and main software into flash.(ask your software friend –if you dare- to make a handy utility for you to do that)

It is common practice to have a neat documented interface in the form of register stack module. Both firmware and software can read/write to update these registers. Apart from this read/write the software and firmware work independantly; nios fetching slowly through the flash(and internal memory for intermediary variables), clock after clock while firmware banging every clock edge at all active registers everywhere.

Wow. Nice of you. Altera should pay you for your services if they haven't already.

I am in Pure/Applied Science area with little programming and digital experience, but if I get the right tutorial, I can learn from there onwards. I am going through your reply very thoroughly, trying to link some of what you said with the "My First Nios Software Design" under IDE environment.

Q1:

When you said "the software can be used to download 'itself' into flash", is this what you mean: "that this can be done if I have the utilities for doing this".

As I am now (without friendly firmware and software engineers around to ask for favours ), I would have to convert the *.SOF to *.POF, and write the *.POF to the flash device?

Q2:

In the Nios Software Design, to run a C program in the Nios configured into the FPGA, I need to "run the project as Nios II hardware" from the Nios IDE environment. So if I have a digital part communicating with the Nios II hardware, do I still have to do this through the Nios IDE?

Q3:

If I just want to use the Nios II in my digital design, is it the "software developer tutorial" or "hardware developer tutorial" that I should be looking at?

Or is the info in Quartus Handbook material which says "Embedded Peripherals" and "SOPC builder" more suitable?

Studying the document is one thing, but finding the right document to study is also another!

Thank you.

Hi hani

A1:

When you are ready to download your software into flash, the NIOS IDE has a tool for doing this (Flash Programmer under the tools menu).

You can carry on using the sof file to configure the hardware but you have to configure the FPGA every time you power it up. If you convert the sof to a pof (usually Quartus does this for you anyway) then you can download the pof to your configuration device (usually serial flash EPCS chip). This then means that the FPGA will configure itself from that memory device each time it powers up - thus saving you the bother of doing it manually.

A2:

Basically Yes.

Sorry I'm not quite sure what you mean by a "digital part" - do you mean another circuit with an interface to your NIOS board. Like the hardware, once you program your software flash device with the software program, it will run itself automatically saving you the bother of downloading it every time. The NIOS IDE will also let you debug your software - set breakpoints, step through code etc - provided you have the debug hardware in your design (which you do in SOPC builder).

A3:

Off the top of my head (without studying the documents again) I would say that you should read the hardware tutorial and then the software one - by the sounds of it you're doing both the hardware design and the software design.

The document on embedded peripherals will be of use when you're really looking at the details of the peripherals or designing new ones but I presume at the moment you're just tyring to get up and running with a "Hello World" type program.

The "SOPC Builder" will probably be of use later when you start playing around with some more complex designs.

Hope this helps.

Stick with it - if you're new to these things it always takes a while to get up and confidently running. Even as an experienced hardware designer I spent a couple of weeks "playing" with NIOS, finding my feet before I started anything approaching a serioous design.

Hi Hani,

I can explain the firmware perspective but not the software side of work, hope others on the forum will add their voice.

--- Quote Start ---

Q1:

When you said "the software can be used to download 'itself' into flash", is this what you mean: "that this can be done if I have the utilities for doing this".

As I am now (without friendly firmware and software engineers around to ask for favours ), I would have to convert the *.SOF to *.POF, and write the *.POF to the flash device?.

--- Quote End ---

You don’t need to do this conversion, quartus by default outputs sof, pof(check that in top menu, device programming files).

You can design a handy nios module on its own, compile it and download it as sof directly into the fpga. This nios module can have just enough fpga memory to do small tasks including downloading pof into flash or downloading any other data.

In steps: build nios in sopc, get ptf, go to IDE and produce some small software as mif file(accommodated inside fpga only), go to quartus and compile to include mif, download sof into the chip and you got a working tiny devil.

You will need to add a flash interface to nios to get it working there.

Your final pof is expected to contain your project including the bootloader, the main software(now too large to be accommodated inside fpga) can be stored in flash as well.

when you power cycle the device, your pof is expected to be loaded into device together with its bootloader. The bootloader then is expected to download the main software which is in the flash.

I guess you may be able to run quartus from within IDE, as your words suggest "run the project as Nios II hardware"

--- Quote Start ---

Q2:

In the Nios Software Design, to run a C program in the Nios configured into the FPGA, I need to "run the project as Nios II hardware" from the Nios IDE environment. So if I have a digital part communicating with the Nios II hardware, do I still have to do this through the Nios IDE?

--- Quote End ---

Again as your words suggest "run the project as Nios II hardware" you may have this tiny luxury not to shuttle between tools. It remains a fact that quartus is the mother compiler! That is responsible for generating the programming files.

I normally do my digital work in quartus. I build nios in sopc tool and go back to quartus, add nios to my project as any submodule and compile and add the mif files(bootloader) as any memory initialisation file.

--- Quote Start ---

Q3:

If I just want to use the Nios II in my digital design, is it the "software developer tutorial" or "hardware developer tutorial" that I should be looking at?

Or is the info in Quartus Handbook material which says "Embedded Peripherals" and "SOPC builder" more suitable?

Studying the document is one thing, but finding the right document to study is also another!

--- Quote End ---

I leave that to other people on the forum. I know there is a jungle of altera pdf files