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You should check the other JTAG signals on the FPGA pins. Check that TMS TCK and TDI are toggling correctly. Pay special attention to the TCK signal. If there are bounces that could be interpreted as additional clock edges by the FPGA then it will cause all kind of problems.
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Here i m attaching the clock signal probed in a DSO when a detect command is issued in UrJTAG, Dont know as to whether this clock is correct or not.Checked with another FT2232, and the clock is exaclty same as attached below. And for the TMS and TDI pin, yes they are toggling, but the TDO is stuck @ 1 as mentioned in the earlier posts.
Regards
Jeebu
Honored Contributor
