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Altera_Forum
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14 years ago

Programming FPGA failing

I m trying to debug a custom built FPGA board developed in my institution, that contains Cyclone IV EP4CE1022C8 FPGA. When programmed using UrJTAG software, it returns a warning: TDO may be stuck at ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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You should check the other JTAG signals on the FPGA pins. Check that TMS TCK and TDI are toggling correctly. Pay special attention to the TCK signal. If there are bounces that could be interpreted as additional clock edges by the FPGA then it will cause all kind of problems.

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Here i m attaching the clock signal probed in a DSO when a detect command is issued in UrJTAG, Dont know as to whether this clock is correct or not.Checked with another FT2232, and the clock is exaclty same as attached below. And for the TMS and TDI pin, yes they are toggling, but the TDO is stuck @ 1 as mentioned in the earlier posts.

Regards

Jeebu