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Honored Contributor
Honored ContributorProgramming FPGA failing
I m trying to debug a custom built FPGA board developed in my institution, that contains Cyclone IV EP4CE1022C8 FPGA. When programmed using UrJTAG software, it returns a warning: TDO may be stuck at ...
Altera_ForumHonored Contributor
Honored ContributorYou should check the other JTAG signals on the FPGA pins. Check that TMS TCK and TDI are toggling correctly. Pay special attention to the TCK signal. If there are bounces that could be interpreted as additional clock edges by the FPGA then it will cause all kind of problems.
