Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Problems with Verilog % Modulo and if-Statements

Hi all, I got a problem with a normally relatively straightforward piece of Verilog code representing some modulo arithmetics and an if-statement. In the code below, the modulo of the r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi all,

thanks a lot for all your very helpful remarks. I will keep them in mind when redesigning the code.

Thanks again,

Jonas