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By the way: What's the deal with the always blocks? Can I rely on the code being executed like e.g. in a C environment or does timing matter here?
In other words: is it guaranteed that the code is properly executed sequentially?
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In a procedural block the commands are executed sequentially.
Timing has no influence on this.
If you use blocking assignments '=', (for example to assign a value to variable Y) and you use Y again to assigna a value to Z. Z is calculated using the new value of Y.
If you use non blocking assignments '<=', (for example to assign a value to variable Y) and you use Y again to assigna a value to Z. Z is calculated using the value of Y before entering in the always statement. In this case Y is updated only when exiting from the always statement.
Hope it helps.
Better to read a Verilog book regarding these aspects.
Honored Contributor
